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1 for more information www.linear.com/ltc3330 typical a pplica t ion fea t ures descrip t ion energy harvesting dc/dc with battery backup the lt c ? 3330 integrates a high voltage energy harvesting power supply plus a dc/ dc converter powered by a primary cell battery to create a single output supply for alternative energy applications. the energy harvesting power supply, consisting of an integrated full-wave bridge rectifier and a high voltage buck converter, harvests energy from piezo - electric, solar, or magnetic sources. the primary cell input powers a buck-boost converter capable of operation down to 1.8 v at its input. either dc/dc converter can deliver en - ergy to a single output. the buck operates when harvested energy is available, reducing the quiescent current draw on the battery to essentially zero. the buck-boost takes over when harvested energy goes away. a low noise ldo post regulator and a supercapacitor balancer are also integrated, accommodating a wide range of output storage configurations. voltage and current settings for both inputs and outputs are programmable via pin-strapped logic inputs. the ltc3330 is available in a 5 mm 5 mm qfn-32 package . a pplica t ions n dual input, single output dc/dcs with input prioritizer energy har vesting input: 3.0 v to 18 v buck dc/ dc primary cell input : 1.8 v to 5.5 v buck- boost dc/ dc n zero battery i q when powering load from harvested energy n ultralow quiescent current: 900na at no-load n low noise ldo post regulator n integrated supercapacitor balancer n up to 50ma of output current n programmable dc/dc and ldo output v oltages, buck uvlo, and buck-boost peak input current n integrated low loss full-wave bridge rectifier n input protective shuntCup to 25ma at v in 20v n 5mm 5mm qfn-32 package n energy harvesting n solar powered systems with primary cell backup n wireless hvac sensors and security devices n mobile asset tracking l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. piezo mide v25w 1f 6v 4.7f, 6v gnd ltc3330 3330 ta01a ac1 v in cap v in2 bat out[2:0] ldo[2:0] ipk[2:0] uv[3:0] ac2 sw swa 22h 22h swb v out ldo_in scap bal ldo_en eh_on pgvout pgldo ldo_out v in3 3v to 18v 4v to 18v solar panel 1f 6v primary cell 1.8v to 5.5v 10f 25v 3 3 3 4 + 1f 6v 2.2f 6v 1.2v to 3.6v 50ma 1.2v to 5v 50ma 10mf 2.5v 10mf 2.5v optional 22f 6v + ? electrical specifications subject to change ltc 3330 3330p
2 for more information www.linear.com/ltc3330 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in low impedance source .......................... C0.3 to 18v* current-fed, i sw = 0a ........................................ 25ma ac1, ac2 ............................................................. 0 to v in bat, v out , v in3 , ldo_in, scap, pgvout, pgldo, eh_on ........................................................ C0.3 to 6v v in2 .................... C0.3v to [lesser of (v in + 0.3v) or 6v] cap ...................... [higher of C0.3v or (v in C 6v)] to v in ldo_out, ldo[2:0], ldo_en .. C0.3v to ldo_in + 0.3v bal ............................................... C0.3v to scap + 0.3v out[2:0] .......... C0.3v to [lesser of (v in3 + 0.3v) or 6v] ipk[2:0] ........... C0.3v to [lesser of (v in3 + 0.3v) or 6v] uv[3:0] ............ C0.3v to [lesser of (v in2 + 0.3v) or 6v] i ac1 , i ac2 .............................................................. 50ma i sw , i swa , i swb , i vout .......................................... 350ma i ldo_out ................................................................. 50ma operating junction t emperature range (notes 2, 3) ............................................ C40c to 125c s torage temperature range .................. C65c to 125c *v in has an internal 20v clamp (note 1) 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1bal scap v in2 uv3 uv2 uv1 uv0 ac1 ldo0 ldo1 ldo2 ldo_in ldo_out ipk2 ipk1 ipk0 out2 out1 out0 eh_on pgvout pgldo v in3 ldo_en ac2 v in cap sw v out swb swa bat t jmax = 125c, ja = 34c/w exposed pad ( pin 33) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3330euh#pbf ltc3330euh#trpbf 3330 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc3330iuh#pbf ltc3330iuh#trpbf 3330 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 3330 3330p
3 for more information www.linear.com/ltc3330 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in buck input voltage range l 3.0 18 v v bat buck-boost input voltage range l 1.8 5.5 v i vin v in quiescent current v in input in uvlo buck enabled, sleeping buck enabled, sleeping buck enabled, not sleeping v in = 2.5v, bat = 0v v in = 4v, bat = 0v v in = 18v, bat = 0v v in = 5v, bat = 0v, i sw1 = 0a (note 4) 450 1150 1650 150 700 1800 2500 250 na na na a i bat bat quiescent current bat input with v in active buck-boost enabled, sleeping buck-boost enabled, not sleeping b at = 1.8 v, v in = 5v bat = 5 v, v in = 0v bat = 5 v , v in = 0v , i swa = i swb = 0 a ( note 4) 900 200 10 1500 330 na na a v ldo_in ldo_in input range l 1.8v 5.5v i ldo_in ldo_in quiescent current ldo_in = 5.0v, i ldo_out = 0a 400 600 na i ldo_out ldo_out leakage current ldo_in = 5.0v, ldo_out = 5.0v 125 na ldo_out regulated ldo output voltage error as a percentage of target l C2.0 2.0 % ldo line regulation (1.8v to 5.5v) ldo_out = 1.2v, 10ma load 2 mv/v ldo load regulation (10a to 10ma) ldo_in = 5.0v, ldo_out = 3.3v 2 mv/ma ldo dropout voltage ldo_out = 3.3v, 10ma load 90 mv ldo current limit ldo_in = 5.0v 50 ma i vout v out leakage current v out = 5.0v 125 na i scap supercapacitor balancer quiescent current scap = 5.0v 165 250 na i source supercapacitor balancer source current scap = 5.0v, bal = 2.4v 10 ma i sink supercapacitor balancer sink current scap = 5.0v, bal = 2.6v 10 ma v bal supercapacitor balance point percentage of scap voltage l 49 50 51 % v inuvlo v in undervoltage lockout thresholds (rising or falling) 3 v level l 2.85 3.00 3.15 v 4v level l 3.80 4.00 4.20 v 5v level l 4.75 5.00 5.25 v 6v level l 5.70 6.00 6.30 v 7v level l 6.65 7.00 7.35 v 8v level l 7.60 8.00 8.40 v 9v level l 8.55 9.00 9.45 v 10v level l 9.50 10.0 10.5 v 11v level l 10.4 11.0 11.6 v 12v level l 11.4 12.0 12.6 v 13v level l 12.3 13.0 13.7 v 14v level l 13.3 14.0 14.7 v 15v level l 14.2 15.0 15.8 v 16v level l 15.2 16.0 16.8 v 17v level l 16.1 17.0 17.9 v 18v level l 17.1 18.0 18.9 v v shunt v in shunt regulator voltage i vin = 1ma 19.0 20.0 21.0 v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. ltc 3330 3330p
4 for more information www.linear.com/ltc3330 symbol parameter conditions min typ max units i shunt maximum protective shunt current 25 ma internal bridge rectifier loss (|v ac1 C v ac2 | C v in ) i bridge = 10a i bridge = 50ma 700 1400 800 1500 900 1600 mv mv internal bridge rectifier reverse leakage current v reverse = 18v 20 na internal bridge rectifier reverse breakdown voltage i reverse = 1a v shunt 30 v v out regulated buck/buck-boost output voltage 1.8v output selected sleep threshold wakeup threshold l l tbd 1.806 1.794 tbd v v 2.5 v output selected sleep threshold wakeup threshold l l tbd 2.508 2.492 tbd v v 2.8 v output selected sleep threshold wakeup threshold l l tbd 2.809 2.791 tbd v v 3.0 v output selected sleep threshold wakeup threshold l l tbd 3.010 2.990 tbd v v 3.3 v output selected sleep threshold wakeup threshold l l tbd 3.311 3.289 tbd v v 3.6 v output selected sleep threshold wakeup threshold l l tbd 3.612 3.588 tbd v v 4.5 v output selected sleep threshold wakeup threshold l l tbd 4.515 4.485 tbd v v 5.0 v output selected sleep threshold wakeup threshold l l tbd 5.017 4.983 tbd v v i peak_buck buck peak switch current 200 250 350 ma i buck available buck output current l 100 ma i ipeak_bb buck-boost peak switch current 250ma target selected 250 350 ma 150ma target selected 150 tbd ma 100ma target selected 100 tbd ma 50ma target selected 50 tbd ma 25ma target selected 25 tbd ma 15ma target selected 15 tbd ma 10ma target selected 10 tbd ma 5ma target selected 5 tbd ma i bb available buck-boost current i ipeak_bb = 250ma, bat = 1.8v, v out = 3.3v l 50 ma r p_buck buck pmos switch on-resistance 1.1 r n_buck buck nmos switch on-resistance 1.3 r p_bb buck-boost pmos switch on-resistance input and output switches 0.5 r n_bb buck-boost nmos switch on-resistance input and output switches 0.5 r p_ldo ldo pmos switch on-resistance ldo_in = 2.5v, i ldo_out = 50ma 7 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. ltc 3330 3330p
5 for more information www.linear.com/ltc3330 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 5v, bat = 3.6v, scap = ov, ldo_in = 0v unless otherwise specified. symbol parameter conditions min typ max units i leak(p) pmos switch leakage buck/buck-boost regulators C20 20 na i leak(n) nmos switch leakage buck/buck-boost regulators C20 20 na maximum buck duty cycle buck/buck-boost regulators l 100 % pgvout threshold as a percentage of v out target l 90 92.5 95 % pgldo threshold as a percentage of ldo_out target l 90 92.5 95 % v ih digital input high voltage pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] l 1.2 v v il digital input low voltage pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] l 0.4 v i ih digital input high current pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] 0 10 na i il digital input low current pins ldo_en, out[2:0], ldo[2:0], ipk[2:0], uv[3:0] 0 10 na v oh pgvout, pgldo, eh_on output high voltage v in3 = 5v, 10a out of pin l 4.6 v v ol pgvout, pgldo, eh_on output low voltage v in3 = 5v, 10a into pin l 0.4 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3330e is tested under pulsed load conditions such that t j t a . the ltc3330e is guaranteed to meet specifications from 0c to 85c. the ltc3330i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient t a and power dissipation pd according to the following formula: t j = t a + (p d ? ja ). note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. ltc 3330 3330p
6 for more information www.linear.com/ltc3330 typical p er f or m ance c harac t eris t ics uvlo rising vs temperature uvlo falling vs temperature v shunt vs temperature total bridge rectifier drop vs bridge current bridge leakage vs temperature bridge frequency response i vin in uvlo vs v in i vin in sleep vs v in i b at in sleep vs b at ltc 3330 3330p
7 for more information www.linear.com/ltc3330 typical p er f or m ance c harac t eris t ics v out load regulation buck/buck- boost v out line regulation buck/buck- boost i peak-buck vs temperature r ds(on) of buck pmos/nmos vs temperature i peak_bb vs temperature (250ma, 150ma, 100ma, 50ma) i peak_bb vs temperature (25ma, 15ma, 10ma, 5ma) v out vs temperature (1.8v, 2.5v, 2.8v, 3.0v) v out vs temperature (3.3v, 3.6v, 4.5v, 5.0v) i vout vs temperature ltc 3330 3330p
8 for more information www.linear.com/ltc3330 typical p er f or m ance c harac t eris t ics buck efficiency vs i load buck-boost efficiency vs i load prioritizer buck-boost to buck transition prioritizer buck to buck-boost transition i scap vs scap supercapacitor balancer source/ sink current r ds(on) of buck-boost pmos/ nmos vs temperature buck switching waveforms buck-boost switching waveforms ltc 3330 3330p
9 for more information www.linear.com/ltc3330 typical p er f or m ance c harac t eris t ics ldo load regulation ldo line regulation ldo current limit r ds(on) of ldo pmos ldo start-up i ldo_in vs ldo_in ldo_out vs temperature ldo load step ltc 3330 3330p
10 for more information www.linear.com/ltc3330 p in func t ions bal (pin 1): supercapacitor balance point. the common node of a stack of two supercapacitors is connected to bal. a source/sink balancing current of up to 10 ma is available. tie bal along with scap to gnd to disable the balancer and its associated quiescent current. scap (pin 2): supply and sense point for supercapacitor balancer. tie the top of a 2- capacitor stack to scap and the middle of the stack to bal to activate balancing. tie scap along with bal to gnd to disable the balancer and its associated quiescent current. v in2 (pin 3): internal low voltage rail to serve as gate drive for buck nmos switch. connect a 4.7f ( or larger) capacitor from v in2 to gnd. this pin is not intended for use as an external system rail. uv3, uv2, uv1, uv 0 (pins 4, 5, 6, 7): uvlo select bits for the buck switching regulator. tie high to v in2 or low to gnd to select the desired uvlo rising and falling thresholds (see table 4). do not float. ac1 (pin 8): input connection for piezoelectric element or other ac source ( used in conjunction with ac2 for differential ac inputs). ac2 (pin 9): input connection for piezoelectric element or other ac sour ce ( used in conjunction with ac1 for differential ac inputs). v in (pin 10): rectified input voltage. a capacitor on this pin serves as an energy reservoir and input supply for the buck regulator. the v in voltage is internally clamped to a maximum of 20v (typical). cap (pin 11): internal rail referenced to v in to serve as gate drive for buck pmos switch. connect a 1f (or larger) capacitor between cap and v in . this pin is not intended for use as an external system rail. sw (pin 12): switch node for the buck switching regula - tor. connect a 22 h or greater external inductor between this node and v out . v out (pin 13): regulated output voltage derived from the buck or buck-boost switching regulator. swb (pin 14): switch node for the buck-boost switching regulator. connect an external inductor between this node and swa of value per table 3. swa (pin 15): switch node for the buck-boost switching regulator. connect an external inductor between this node and swb of value per table 3. b at (pin 16): input for battery. bat serves as the input to the buck-boost switching regulator. ipk0, ipk1, ipk 2 (pins 17, 18, 19): ipeak select bits for the buck-boost switching regulator . ti e high to v in3 or low to gnd to select the desired ipeak ( see table 3). do not float. ldo_out (pin 20): regulated ldo output. this output can be used as a quiet supply. one mode is provided to run the ldo as a current limited switch to alternately power up and power down circuitry without low power modes. ldo_in (pin 21): input voltage for the ldo regulator. ldo2, ldo1, ldo 0 (pins 22, 23, 24): ldo voltage select bits. tie high to ldo_in or low to gnd to select the desired ldo_out voltage (see table 2). do not float. ldo_en (pin 25): ldo enable input. active high input with logic levels referenced to ldo_in. do not float. v in3 ( pin 26): internal low voltage rail used by the priori - tizer. connect a 1f ( or larger) capacitor from v in3 to gnd. this pin is not intended for use as an external system rail. pgldo (pin 27): power good output for ldo_out. logic level output referenced to an internal maximum rail (see operation). pgldo transitioning high indicates 92.5% ( typical) regulation has been reached on ldo _ out. pgldo remains high until ldo_out falls to 90.0% ( typical) of the programmed regulation point. pgvout ( pin 28): power good output for v out . logic level output referenced to an internal maximum rail (see operation). pgvout transitioning high indicates regula - tion has been reached on v out (v out = sleep rising). pgvout remains high until v out falls to 92.5% (typical) of the programmed regulation point. bat_on (pin 29): switcher status. logic level output referenced to v in3 . eh_on is high when the buck switch- ing regulator is in use. it is pulled low when buck-boost switching regulator is in use. ltc 3330 3330p
11 for more information www.linear.com/ltc3330 out0, out1, out 2 (pins 30, 31, 32): v out voltage select bits. tie high to v in3 or low to gnd to select the desired v out (see table 1). do not float. p in func t ions gnd ( exposed pad pin 11): ground. the exposed pad must be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the ltc3330. b lock diagra m 3330 bd bandgap reference internal rail generation prioritzer uvlo uvlo_set sleep v in v ref ac1 20v 10 8 ac2 bat 9 16 eh_on sleep ilim_set v ref pgvout pgldo 29 28 27 ? + ? + sleep 0.9*v ref v ref ? + ? + 0.925*v ref cap 11 sw v in2 gnd 33 swa swb ldo_in v out 15 14 13 21 ldo_out scap bal 20 1 2 v in3 26 buck-boost control ilim_set uvlo_set 12 3 3 3 32, 31, 30 22, 23, 24 4 4, 5, 6, 7 uv[3:0] 3 19, 18, 17 ipk[2:0] out[2:0] ldo[2:0] buck control ldo_en 25 ? + ltc 3330 3330p
12 for more information www.linear.com/ltc3330 o pera t ion modes of operation the following four tables detail all programmable settings on the ltc3330. table 1. output voltage selection out2 out1 out2 v out 0 0 0 1.8v 0 0 1 2.5v 0 1 0 2.8v 0 1 1 3.0v 1 0 0 3.3v 1 0 1 3.6v 1 1 0 4.5v 1 1 1 5.0v table 2. ldo voltage selection ldo2 ldo1 ldo0 ldo_out 0 0 0 1.2v 0 0 1 1.5v 0 1 0 1.8v 0 1 1 2.0v 1 0 0 2.5v 1 0 1 3.0v 1 1 0 3.3v 1 1 1 = ldo_in table 3. i lim selection ipk 2 ipk 1 ipk 0 i lim l min 0 0 0 5ma 1100h 0 0 1 10ma 560h 0 1 0 15ma 360h 0 1 1 25ma 220h 1 0 0 50ma 110h 1 0 1 100ma 56h 1 1 0 150ma 36h 1 1 1 250ma 22h table 4. v in uvlo threshold selection uv3 uv2 uv1 uv0 uvlo rising uvlo falling 0 0 0 0 4v 3v 0 0 0 1 5v 4v 0 0 1 0 6v 5v 0 0 1 1 7v 6v 0 1 0 0 8v 7v 0 1 0 1 8v 5v 0 1 1 0 10v 9v 0 1 1 1 10v 5v 1 0 0 0 12v 11v 1 0 0 1 12v 5v 1 0 1 0 14v 13v 1 0 1 1 14v 5v 1 1 0 0 16v 15v 1 1 0 1 16v 5v 1 1 1 0 18v 17v 1 1 1 1 18v 5v ltc 3330 3330p
13 for more information www.linear.com/ltc3330 overview the ltc3330 combines a buck switching regulator and a buck-boost switching regulator to produce an energy harvesting solution with battery backup. the converters are controlled by a prioritizer that selects which converter to use based on the availability of a battery and/ or harvestable energy. if harvested energy is available the buck regula - tor is active and the buck-boost is off. with an optional ldo and supercapacitor balancer and an array of different configurations the ltc3330 suits many applications. buck converter the synchronous buck converter is an ultralow quiescent current power supply tailored to energy harvesting applica - tions. it is designed to interface directly to a piezoelectric or alternative a/c power source, rectify the input voltage, and store harvested energy on an external capacitor while maintaining a regulated output voltage. it can also bleed off any excess input power via an internal shunt regulator. internal bridge rectifier an internal full-wave bridge rectifier accessible via the differential ac1 and ac2 inputs rectifies ac sources such as those from a piezoelectric element. the rectified output is stored on a capacitor at the v in pin and can be used as an energy reservoir for the buck converter. the bridge rectifier has a total drop of about 800 mv with typical piezo-generated currents (~10 a), but is capable of carrying up to 50 ma. either side of the bridge can be operated independently as single-ended ac or dc inputs. undervoltage lockout when the voltage on v in rises above the uvlo rising threshold the buck converter is enabled and charge is transferred from the input capacitor to the output capaci - tor. when the input capacitor voltage is depleted below the uvlo falling threshold the buck converter is disabled. these thresholds can be set according to table 4 which offers uvlo rising thresholds from 4 v to 18 v with large or small hysteresis windows ( see table 4). extremely low o pera t ion figure 1. ideal v in , v in2 and cap relationship quiescent current (450 na typical) in uvlo allows energy to accumulate on the input capacitor in situations where energy must be harvested from low power sources. internal rail generation tw o internal rails, cap and v in2 , are generated from v in and are used to drive the high side pmos and low side nmos of the buck converter, respectively. additionally the v in2 rail serves as logic high for the uvlo threshold select bits uv[3:0]. the v in2 rail is regulated at 4.8 v above gnd while the cap rail is regulated at 4.8 v below v in . these are not intended to be used as external rails. bypass capaci- tors are connected to the cap and v in2 pins to serve as energy reservoirs for driving the buck switches. when v in is below 4.8 v, v in2 is equal to v in and cap is held at gnd. figure 1 shows the ideal v in , v in2 and cap relationship. v in (v) 0 voltage (v) 18 12 14 16 10 2 4 8 6 0 10 5 3330 f01 15 v in v in2 cap buck operation the buck regulator uses a hysteretic voltage algorithm to control the output through internal feedback from the v out sense pin. the buck converter charges an output capacitor through an inductor to a value slightly higher than the regulation point. it does this by ramping the inductor current up to 260 ma through an internal pmos switch and then ramping it down to 0 ma through an internal nmos switch. this efficiently delivers energy to the output capacitor. the ramp rate is determined by v in , ltc 3330 3330p
14 for more information www.linear.com/ltc3330 o pera t ion v out , and the inductor value. when the buck brings the output voltage into regulation the converter enters a low quiescent current sleep state that monitors the output volt - age with a sleep comparator. during this operating mode load current is provided by the output capacitor. when the output voltage falls below the regulation point the buck regulator wakes up and the cycle repeats. this hysteretic method of providing a regulated output reduces losses associated with fet switching and maintains an output at light loads. the buck delivers a minimum of 100 ma of average load current when it is switching. v out can be set from 1.8v to 5v via out[2:0] (see table 1). when the sleep comparator signals that the output has reached the sleep threshold the buck converter may be in the middle of a cycle with current still flowing through the inductor. normally both synchronous switches would turn off and the current in the inductor would freewheel to zero through the nmos body diode, but the nmos switch is kept on to prevent the conduction loss that would occur in the diode if the nmos were off. if the pmos is on when the sleep comparator trips the nmos will turn on immediately in order to ramp down the current. if the nmos is on it will be kept on until the current reaches zero. though the quiescent current when the buck is switching is much greater than the sleep quiescent current, it is still a small percentage of the average inductor current which results in high efficiency over most load conditions. the buck operates only when sufficient energy has been ac - cumulated in the input capacitor and the length of time the converter needs to transfer energy to the output is much less than the time it takes to accumulate energy. thus, the buck operating quiescent current is averaged over a long period of time so that the total average quiescent current is low. this feature accommodates sources that harvest small amounts of ambient energy. buck-boost c onver ter the buck - boost uses the same hysteretic voltage algorithm as the buck to control the output, v out , with the same sleep comparator. the buck-boost has three modes of operation: buck, buck-boost, and boost. an internal mode comparator determines the mode of operation based on bat and v out . figure 2 shows the four internal switches of the buck-boost converter . in each mode the inductor current is ramped up to ipeak. this ipeak value is pro- grammable via ipk[2:0] and ranges from 5 ma to 250ma (see table 3). in buck mode m4 is always on and m3 is always off. the inductor current is ramped up through m1 to ipeak and down to 0 ma through m2. in boost mode m1 is always on and m2 is always off. the inductor current is ramped up to ipeak when m3 is on and is ramped to 0 ma when m4 is on as v out is greater than bat in boost mode. buck- boost mode is very similar to boost mode in that m1 is always on and m2 is always off. if bat is less than v out the inductor current is ramped up to ipeak through m3. when m4 turns on the current in the inductor will start to ramp down. however, because bat is close to v out and m1 and m4 have finite on-resistance the current ramp will exhibit a slow exponential decay, lowering the aver - age current delivered to v out . for this reason the lower current threshold is set to ipeak/2 in buck-boost mode to maintain high average current to the load. if b at is greater than v out in buck-boost mode the inductor cur- rent still ramps up to ipeak and down to ipeak/2. it can still ramp down if bat is greater than v out because the final value of the current in the inductor is (v in C v out )/ (r on1 + r on4 ). if bat is exactly ipeak /2?(r on1 + r on4 ) above v out the inductor current will not reach the ipeak/2 threshold and switches m1 and m4 will stay on all the time. for higher bat voltages the mode comparator will switch the converter to buck mode. m1 and m4 will remain on for bat voltages up to v out + ipeak?(r on1 + r on4 ). at figure 2: buck-boost power switches 3330 f02 swa swb m1 bat m4 v out m3 m2 ltc 3330 3330p
15 for more information www.linear.com/ltc3330 this point the current in the inductor is equal to ipeak and the ipeak comparator will trip turning off m1 and turn- ing on m2 causing the inductor current to ramp down to izero, completing the transition from buck-boost mode to buck mode. v out power good a power good comparator is provided for the v out out- put. it transitions high the first time the ltc3330 goes to sleep, indicating that v out has reached regulation. it transitions low when v out falls to 92.5% ( typical) of its value at regulation. the pgvout output is referenced to an internal rail that is generated to be the highest of v in2 , bat , and v out less a schottky diode drop. prioritizer the input prioritizer on the ltc3330 decides whether to use the energy harvesting input or the battery input to power v out . if a battery is powering the buck-boost converter and harvested energy causes a uvlo rising transition on v in , the prioritizer will shut off the buck-boost and turn on the buck, orchestrating a smooth transition that maintains regulation of v out . when harvestable energy disappears, the prioritizer will first poll the battery voltage. if the battery voltage is above 1.8 v the prioritizer will switch back to the buck-boost while maintaining regulation. if the bat- tery voltage is below 1.8 v the buck-boost is not enabled and v out cannot be supported until harvestable energy is again available. if either bat or v in is grounded, the prioritizer allows the other input to run if its input is high enough for operation. when the prioritizer selects the v in input the current on the bat input drops to zero. however, if the voltage on bat is higher than v in2 , 150 na ( typical) will appear as quiescent current on bat due to internal level shifting. this only affects a small range of battery voltages and uvlo settings. a digital output, eh_on, is low when the prioritizer has selected the bat input and is high when the prioritizer has selected the v in input. the eh_on output is referenced to v in3 . low drop out regulator an integrated low drop out regulator ( ldo) is available with its own input, ldo_in. it will regulate ldo_out to seven different output voltages based on the ldo[2:0] pins. an eighth mode is provided to turn the ldo into a current- limited switch in which the pmos is always on. ldo_en enables the ldo when high and when low eliminates all quiescent current on ldo_in. the ldo is designed to provide 50 ma over a range of ldo_in and ldo_out combinations. a current limit set above 50 ma is available to dial back the current if the output is grounded or the load demands more than 50 ma. the ldo also features a 1ms soft-start for smooth output start-up. a power good signal on the pgldo pin indicates when the voltage at ldo_out rises above 92.5% ( typical) of its final value, or after tripped, when the ldo_out falls below 90.0% of that value. the pgldo output is referenced to an internal rail that is generated to be the highest of v in2 , bat , and v out less a schottky diode drop. supercapacitor an integrated supercapacitor balancer with 165 na of quiescent current is available to balance a stack of two supercapacitors. typically the input, scap, will tie to v out to allow for increased energy storage at v out with supercapacitors. the bal pin is tied to the middle of the stack and can source and sink 10 ma to regulate the bal pin s voltage to half that of the scap pins voltage. to disable the balancer and its associated quiescent current the scap and bal pins can be tied to ground. o pera t ion ltc 3330 3330p
16 for more information www.linear.com/ltc3330 typical a pplica t ions ltc 3330 3330p
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19 for more information www.linear.com/ltc3330 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) ltc 3330 3330p
20 for more information www.linear.com/ltc3330 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2013 lt 0313 ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3330 ups system for wireless mesh networks with output supercapacitor energy storage r ela t e d p ar t s typical a pplica t ion part number description comments lt1389 nanopower precision shunt voltage reference 800na operating current, 1.25v/2.5v/4.096v ltc1540 nanopower comparator with reference 0.3a i q , drives 0.01f, adjustable hysteresis, 2v to 11v input range lt3009 3a i q , 20ma low dropout linear regulator low 3a i q , 1.6v to 20v range, 20ma output current LTC3108 ultralow voltage step-up converter and power manager operates from 20mv inputs, ldo, reserve output, power good ltc3109 auto-polarity, ultralow voltage step-up converter and power manager operates from 30mv inputs, auto-polarity architecture, ldo, energy storage capability, power good ltc3388-1/ ltc3388-3 20v high efficiency nanopower step-down regulator 860na i q in sleep, 2.7v to 20v input, v out : 1.2v to 5.0v, enable and standby pins ltc3588-1 piezoelectric energy harvesting power supply <1a i q in regulation, 2.7v to 20v input range, integrated bridge rectifier ltc3588-2 piezoelectric energy harvesting power supply <1a i q in regulation, uvlo rising = 16v, uvlo falling = 14v, v out = 3.45v, 4.1v, 4.5v, 5.0v ltc4070 li-ion/polymer shunt battery charger system 450na i q , 1% float voltage accuracy, 50ma shunt current 4.0v/4.1v/4.2v ltc4071 li-ion/polymer shunt battery charger system with low battery disconnect 550na i q , 1% float voltage accuracy, 50ma shunt current 4.0v/4.1v/4.2v, 2.7v or 3.2v batter y disconnect levels 1f 6v 4.7f, 6v gnd ltc3330 3330 ta02 ac1 v in cap v in2 ac2 sw swa 100h 100h swb v out scap bal pgvout eh_on v in3 1f 6v li-soci 2 3.65v 10f 25v uv3 uv2 uv1 uv0 bat ipk2 ipk1 ipk0 out2 out1 out0 + 1f 6v v out = 3.6v for eh_on = 1 v out = 2.5v for eh_on = 0 10mf 2.5v 10mf 2.5v v supply gnd linear technology dc9003a-a/b dust mote for wireless mesh networks pgood ehorbat t x 22f 6v piezo mide v25w ltc 3330 3330p

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